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NJW4154 - 1 - ver.2013-03-29 switching regulator ic for buck converter current mode control w/ 40v/3a mosfet general description package outline features current mode control external clock synchronization wide operating voltage range 4.5v to 40v switching current 4.5a min. pwm control built-in compensation circuit correspond to ceramic capacitor (mlcc) oscillating frequency 300khz typ. (a ver.) soft start function 4ms typ. uvlo (under voltage lockout) over current protection (hiccup type) thermal shutdown protection power good function (NJW4154gm1 only) standby function package outline NJW4154gm1 : hsop8 NJW4154dl3 : to-252-5 product classification part number version oscillation frequency power good package operating temperature range NJW4154gm1-a a 300khz typ. hsop8 general spec. -40 c to +85 c NJW4154dl3-a a 300khz typ. to-252-5 general spec. -40 c to +85 c the NJW4154 is a buck converter with 40v/3a mosfet. it corresponds to high oscillating frequency, and low esr output capacitor (mlcc) within wide input range from 4.5v to 40v. therefore, the NJW4154 can realize downsizing of applications with a few external parts so that adopts current mode control. also, it has a soft start function , external clock synchronization, over current protection and thermal shutdown circuit. it is suitable for supplying power to a car accessory, office a utomation equipmen t , industrial instrument and so on. NJW4154dl3 NJW4154gm1
NJW4154 - 2 - ver.2013-03-29 pin configuration block diagram po w e r go o d control logic v + in- er ? amp buffer ocp current sense tsd vref sof t start uv lo slope comp. 0.8v s q r osc gnd high: on low : off(standby) en/sync sw pwm sync enable (standby) pg NJW4154gm1 only low frequency contr ol 100k ? pin function 1. v + 2. sw 3. gnd 4. in- 5. en/sync 1 2 3 4 5 3 1 4 3 2 8 5 6 7 exposed pad on backside connect to gnd NJW4154gm1-a pin function 1. sw 2. sw 3. gnd 4. pg 5. in- 6. en/sync 7. v + 8. v + NJW4154dl3-a
NJW4154 - 3 - ver.2013-03-29 absolute maximum ratings (ta=25c) parameter symbol maximum ratings unit supply voltage v + +45 v v + - sw pin voltage v v-sw +45 v en/sync pin voltage v en/sync +45 v in- pin voltage v in- -0.3 to +6 v power good pin voltage (*1) v pg -0.3 to +6 v 790 (*2) hsop8 2,500 (*3) 1,190 (*4) power dissipation p d to-252-5 3,125 (*3) mw junction temperature range tj -40 to +150 c operating temperature range t opr -40 to +85 c storage temperature range t stg -40 to +150 c (*1): apply only the NJW4154gm1. (*2): mounted on glass epoxy board. (76.2114.31.6mm:based on eia/jdec standard, 2layers) (*3): mounted on glass epoxy board. (76.2114.31.6mm:based on eia/jdec standard, 4layers) (for 4layers: applying 74.274.2mm inner cu area and a thermal via hall to a board based on jedec standard jesd51-5) (*4): mounted on glass epoxy board. (76.2114.31.6mm:based on eia/jdec standard size, 2layers, cu area 100mm 2 ) recommended operating conditions parameter symbol min. typ. max. unit supply voltage v + 4.5 ? 40 v power good pin voltage (*5) v pg 0 ? 5.5 v external clock input range f sync 290 ? 500 khz (*5): apply only the NJW4154gm1.
NJW4154 - 4 - ver.2013-03-29 electrical characteristics (unless otherwise noted, v + =v en./sync =12v, ta=25 c) parameter symbol test condition min. typ. max. unit under voltage lockout block on threshold voltage v t_on v + = l h 4.2 4.4 4.5 v off threshold voltage v t_off v + = h l 4.1 4.3 4.4 v hysteresis voltage v hys 70 90 ? mv soft start block soft start time t ss v b =0.75v 2 4 8 ms oscillator block oscillation frequency f osc a version, v in- =0.7v 270 300 330 khz oscillation frequency ocp operates f osc_lim a version, v in- =0.4v ? 100 ? khz oscillation frequency deviation (supply voltage) f dv v + =4.5v to 40v ? 1 ? % oscillation frequency deviation (temperature) f dt ta = - 4 0 c to +85 c ? 5 ? % error amplifier block reference voltage v b -1.0% 0.8 +1.0% v input bias current i b -0.1 ? +0.1 a pwm comparate block maximum duty cycle m ax d uty v in- =0.7v 88 93 ? % minimum on time1 (use built-in oscillator) t on-min1 ? 250 340 ns minimum on time2 (use ext clk) t on-min2 f sync =400khz ? 170 250 ns ocp block cool down time t cool ? 25 ? ms output block output on resistance r on i sw =3a ? 0.15 0.3 ? switching current limit i lim 4.5 6 7.5 a sw leak current i leak v en/sync =0v, v + =45v, v sw =0v ? ? 4 a
NJW4154 - 5 - ver.2013-03-29 electrical characteristics (unless otherwise noted, v + =v en/sync =12v, ta=25 c) parameter symbol test condition min. typ. max. unit standby control / sync block en/sync pin high threshold voltage v thh_en/sync v en/sync = l h 1.6 ? v + v en/sync pin low threshold voltage v thl_en/sync v en/sync = h l 0 ? 0.5 v input bias current (en/sync pin) i en v en/sync =12v ? 170 250 a power good block (*6) high level detection voltage v thh_pg measured at in- pin 105 110 115 % high level detection voltage v thl_pg measured at in- pin 85 90 95 % hysterisis region v hys_pg ? 2 ? % power good on resistance r on_pg i pg =10ma ? 37 50 ? leak current at off state i leak_pg v pg =6v ? ? 0.1 a general characteristics quiescent current i dd r l =no load, v in- =0.7v ? 3.5 4.2 ma standby current i dd_stb v en/sync =0v ? ? 3 a (*6): apply only the NJW4154gm1.
NJW4154 - 6 - ver.2013-03-29 typical applications sw pg gnd in- c fb r2 c out l sbd NJW4154 v in c in1 r1 v out r fb v + en/ sy nc en/ sy nc high: on low: off (standby) po w e r go o d ( NJW4154gm1 only) c in2
NJW4154 - 7 - ver.2013-03-29 typical characteristics reference voltage vs. supply voltage (ta=25c) 0.79 0.795 0.8 0.805 0.81 0 10203040 supply voltage v + (v) reference voltage v b (v) oscillation frequency vs. supply voltage (a ver., v in- =0.7v, ta=25c) 290 292 294 296 298 300 302 304 306 308 310 0 10203040 supply voltage v + (v) oscillation frequnecny f osc (khz) quiescent current vs. supply voltage (r l =no load, v in- =0.7v, ta=25c) 0 1 2 3 4 5 6 0 10203040 supply voltage v + (v) quiescent current i dd (ma)
NJW4154 - 8 - ver.2013-03-29 typical characteristics reference voltage vs. temperature (v + =12v) 0.790 0.795 0.800 0.805 0.810 -50 -25 0 25 50 75 100 125 150 ambient temperature ta (c) reference voltage v b (v) switching current limit vs. temperature 3 4 5 6 7 8 -50 -25 0 25 50 75 100 125 150 ambient temperature ta (c) switching current limit i lim (a) v + =40v v + =12v v + =5v output on resistance vs. temperature (i sw =3a) 0 0.05 0.1 0.15 0.2 0.25 0.3 -50 -25 0 25 50 75 100 125 150 ambient temperature ta (c) output on resistance r on ( ? ) v + =12v v + =5v v + =40v soft start time vs. temperature (v + =12v, v b =0.75v) 2 3 4 5 6 7 8 -50-25 0 255075100125150 ambient temperature ta (c) soft start time tss (ms) oscillation frequency vs temperature (a ver., v + =12v, v in- =0.7v) 270 280 290 300 310 320 330 -50 -25 0 25 50 75 100 125 150 ambient temperature ta (c) oscillation frequency fosc (khz) under voltage lockout voltage vs. temperature 4.1 4.15 4.2 4.25 4.3 4.35 4.4 4.45 4.5 -50 -25 0 25 50 75 100 125 150 ambient temperature ta (c) threshold voltage (v) v t_on v t_off
NJW4154 - 9 - ver.2013-03-29 typical characteristics quiescent current vs. temperature (r l =no load, v in- =0.7v) 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 -50 -25 0 25 50 75 100 125 150 ambient temperature ta (c) quiescent current i dd (ma) v + =12v v + =40v v + =4.5v standby current vs. temperature (v en/sync =0v) 0 1 2 3 4 5 6 7 8 9 10 -50 -25 0 25 50 75 100 125 150 ambient temperature ta (c) standby current i dd_stb (a) v + =40v v + =12v v + =4.5v switching leak current vs. temperature (v + =45v , v en/sync =0v , v sw =0v) 0 1 2 3 4 5 6 7 8 9 10 -50 -25 0 25 50 75 100 125 150 ambient temperature ta (c) switching leak current i leak (a) maximum duty cycle vs. temperature (v + =12v, v in- =0.7v) 88 89 90 91 92 93 94 95 96 97 98 99 100 -50 -25 0 25 50 75 100 125 150 ambient temperature ta (c) maximum duty cycle m ax d uty (%) minimum on time1 vs. temperature (v + =12v) 160 180 200 220 240 260 280 300 320 340 -50 -25 0 25 50 75 100 125 150 ambient temperature ta (c) minimum on time1 t on-min1 (ns)
NJW4154 - 10 - ver.2013-03-29 pin descriptions pin number pin name hsop8 to-252-5 function sw 1 2 2 switch output pin of power mosfet gnd 3 3 gnd pin pg 4 ? power good pin. an open drain output that goes high impedance when the in- pin voltage is stable around 10%. (only hsop8 pkg) in- 5 4 output voltage detecting pin connects output voltage through the resistor divider tap to this pin in order to voltage of the in- pin become 0.8v. en/sync 6 5 standby control pin the en/sync pin internally pulls down with 100k ? . normal operation at the time of high level . standby mode at the time of low level or open. moreover, it operates by inputting clock signal at the oscillatory frequency that synchronized with the input signal. v + 7 8 1 power supply pin for power line exposed pad ? ? connect to gnd (only hsop8 pkg) technical information njw 41 5 4 application manual
NJW4154 - 11 - ver.2013-03-29 description of block features 1. basic functions / features error amplifier section (er ? amp) 0.8v1% precise reference voltage is connecte d to the non-inverted input of this section. to set the output voltage, connects converter's output to inve rted input of this section (in- pin). if requires output voltage over 0.8v, inserts resistor divider. because the optimized compensation circuit is built-in , the application circuit can be composed of minimum external parts. pwm comparator section (pwm), oscillation circuit section (osc) the NJW4154 uses a constant frequency, current mode st ep down architecture. the oscillation frequency is 300khz (typ.) at a version. the pwm signal is output by feedback of output voltage and slope compensation switching current at the pwm comparator block. the maximum duty ratio is 93% (typ.). the minimum on time is limited to 250nsec (typ.) at using internal oscillator or 170nsec (typ.) at external synchronization. the buck converter of on time is decided the following formula. [] s f v v ton osc in out = v in shows input voltage and v out shows output voltage. when the on time becomes below in t on-min , in order to maintain output voltage at a stable state, change of duty or pulse skip operation may be performed. power mosfet (sw output section) the power is stored in the inductor by the switch operati on of built-in power mosfet. the output current is limited to 4.5a(min.) the overcurrent protection function. in case of step-down converter, the forward direction bias voltage is generated with inductance current that flows into the ex ternal regenerative diode when mosfet is turned off. the sw pin allows voltage between the pv + pin and the sw pin up to +45v. however, you should use an schottky diode that has low saturation voltage. power supply, gnd pin (v + and gnd) in line with switching element drive, current flows into the ic according to frequency. if the power supply impedance provided to the power supply circuit is high, it will not be possible to take advantage of ic performance due to input voltage fluctuation. therefore insert a bypass capacitor close to the v + pin ? the gnd pin connection in order to lower high frequency impedance. technical information njw 41 5 4 application manual
NJW4154 - 12 - ver.2013-03-29 description of block features (continued) 2. additional and protection functions / features under voltage lockout (uvlo) the uvlo circuit operating is released above v + =4.4v(typ.) and ic operation starts. when power supply voltage is low, ic does not operate because the uvlo circuit operates . there is 90mv(typ.) width hysteresis voltage at rise and decay of power supply voltage. hysteresis prevent s the malfunction at the time of uvlo operating and releasing. soft start function (soft start) the output voltage of the converter gradually rises to a set value by the soft start function. the soft start time is 4ms (typ.). it is defined with the time of the error amplif ier reference voltage becoming from 0v to 0.75v. the soft start circuit operates after the release uvlo and/or recovery from thermal shutdown. sw pin 0.8v on off vref, in- pin voltage osc wavef orm steady operaton uvlo(4.4v typ.) release, standby, recover from thermal shutdow n soft start effective period to v b =0.8v soft start time: tss=4ms(typ.) to v b =0.75v fig. 1. startup timing chart technical information njw 41 5 4 application manual
NJW4154 - 13 - ver.2013-03-29 description of block features (continued) over current protection circuit (ocp) NJW4154 contains overcurrent protection circuit of hiccup architecture. the overcurrent protection circuit of hiccup architecture is able to decrease heat generation at the overload. the NJW4154 output returns automatically along wi th release from the over current condition. at when the switching current becomes i lim or more, the overcurrent protecti on circuit is stopped the mosfet output. the switching output holds low level dow n to next pulse output at ocp operating. when in- pin voltage becomes 0.5v or less, it operates with 100khz (typ.). at the same time starts pulse counting, and stops the switching operation when the overcurrent detection continues approx 1ms. after NJW4154 switching operation was stopped, it restarts by soft start function after the cool down time of approx 25ms (typ.). sw pin on off sw itching current i lim 0 0.8v 0.5v 0v in- pin voltage ocp operates oscillation frequency f osc_lim =100khz typ. cool dow n time :25ms typ. oscillation frequency fosc=300khz typ. static status detec t overcurrent sof t start pu ls e b y pu ls e pulse count :about 1ms fig. 2. timing chart at over current detection thermal shutdown function (tsd) when junction temperature of the NJW4154 exceeds the 160c*, internal thermal shutdown circuit function stops sw function. when junction temperature decreases to 145c* or less, sw operation returns with soft start operation. the purpose of this function is to prevent malfunctioning of ic at the high junction temperature. therefore it is not something that urges positive use. you should make sure to operate within the junction temperature range rated (150 c). (* design value) standby function the NJW4154 stops the operating and becomes standby stat us when the en/sync pin becomes less than 0.5v. the en/sync pin internally pulls down with 100k ? , therefore the NJW4154 becomes standby mode when the en/sync pin is open. you s hould connect this pin to v + when you do not use standby function. technical information njw 41 5 4 application manual
NJW4154 - 14 - ver.2013-03-29 description of block features (continued) external clock synchronization by inputting a square wave to en/sync pin, can be synchronized to an external frequency. you should fulfill the following specification about a square wave. input frequency : 290khz to 500khz duty cycle : 20% to 80% voltage magnitude : 1.6v or more at high level 0.5v or less at low level the trigger of the switching operating at the external sync hronized mode is detected to the rising edge of the input signal. at the time of switching operation from standby or asynchronous to synchronous operation, it has set a delay time approx 20 s to 30 s in order to prevent malfunctions. (fig. 3.) standby delay time sw pin on off external clock synchronization en/ sy nc p in high low fig. 3. switching operation by external synchronized clock power good function (NJW4154gm1 only) it monitors the output status and outputs a signal from pg pin that internally connected to open drain mosfet. the power good pin goes high impedance when t he in- pin voltage is stable around 10%(typ.) of error amplifier reference voltage. a low on the pin indicates that the in- pin voltage is out of the setting voltage. to prevent malfunction of the power good output, it has hysterisis 2%(typ.) and the delay time approx 20 s to 30 s against the in- pin voltage changes. technical information njw 41 5 4 application manual
NJW4154 - 15 - ver.2013-03-29 application information inductors because a large current flows to the inductor, you should se lect the inductor with the la rge current capacity not to saturate. optimized inductor value is determ ined by the input voltage and output voltage. the optimized inductor value: (it is a reference value.) v iin =12v v out =3.3v : l <= 3.5 h v iin =12v v out =5.0v : l <= 4.7 h v iin =24v v out =5.0v : l <= 3.5 h you should set the inductor as a guide from above mentioned value to half value. reducing l decreases the size of the inductor. howeve r a peak current increases and adversely affects the efficiency. (fig. 4.) moreover, you should be aware that the output current is limited because it becomes easy to operating to the overcurrent limit. the peak current is decided the following formula. () ] a [ f v l v v v i osc in out out in l ? = ? ] a [ i i ipk l out 2 ? + = output current i out indunctor ripple current ? i l 0 current t on t off peak current i pk indunctor ripple current ? i l peak current i pk t on t off reducing l value increasing l value fig. 4. inductor current state transition (continuous conduction mode) technical information njw 41 5 4 application manual
NJW4154 - 16 - ver.2013-03-29 application information (continued) catch diode when the switch element is in off cycle, power stored in the inductor flows via the catch diode to the output capacitor. therefore during each cycle current flows to the diode in response to load current. because diode's forward saturation voltage and current accumulation caus e power loss, a schottky barrier diode (sbd), which has a low forward saturation voltage, is ideal. an sbd also has a short reverse recovery time. if the reve rse recovery time is long, through current flows when the switching transistor transitions from off cycle to on cycle. this current may lower efficiency and affect such factors as noise generation. input capacitor transient current flows into the input section of a switch ing regulator responsive to frequency. if the power supply impedance provided to the power supply circuit is large, it will not be possible to take advantage of the NJW4154 performance due to input voltage fluctuation. therefore in sert an input capacitor as close to the mosfet as possible. a ceramic capacitor is the optimal for input capacitor. the effective input current can be expressed by the following formula. () ] a [ v v v v i i in out in out out rms ? = in the above formula, the maximum current is obtained when v in = 2 v out , and the result in this case is i rms = i out (max) 2. when selecting the input capacitor, carry out an evaluati on based on the application, and use a capacitor that has adequate margin. output capacitor an output capacitor stores power from the induc tor, and stabilizes voltage provided to the output. because NJW4154 corresponds to the output capacitor of low esr, the ceramic capa citor is the optimal for compensation. the optimized capacitor value: (it is a reference value.) v out =3.3v : c out >= 100 f v out =5.0v : c out >= 47 f in addition, you should consider vari ed characteristics of capacitor (a frequency characteristic, a temperature characteristic, a dc bias characteristic and so on) and unevenness peculiar to a capacitor supplier enough. therefore when selecting a capacitors, you should co nfirm the characteristics with supplier datasheets. when selecting an output capacitor, you must consider equi valent series resistance (esr ) characteristics, ripple current, and breakdown voltage. the output ripple noise can be expr essed by the following formula. ] v [ i esr v l ) p p ( ripple ? = ? the effective ripple current that flows in a capacitor (i rms ) is obtained by the following equation. ] arms [ i i l rms 3 2 ? = technical information njw 41 5 4 application manual
NJW4154 - 17 - ver.2013-03-29 application information (continued) setting output voltage, compensation capacitor the output voltage v out is determined by the relative resistances of r1, r2. the current that flows in r1, r2 must be a value that can ignore the bias current that flows in er amp. ] v [ v r r v b out ? ? ? ? ? ? + = 1 1 2 the zero points are formed with r2 and c fb , and it makes for the phase compensation of NJW4154. the zero point is shown the following formula . ] hz [ c r f fb z = 2 2 1 1 you should set the zero point as a guide from 50khz to 70khz. technical information njw 41 5 4 application manual
NJW4154 - 18 - ver.2013-03-29 application information (continued) board layout in the switching regulator application, because the cu rrent flow corresponds to the oscillation frequency, the substrate (pcb) layout becomes an important. you should attempt the transition voltage decrease by maki ng a current loop area minimize as much as possible. therefore, you should make a current flowing line thick and short as much as possible. fig.5. shows a current loop at step-down converter. especially, should lay out high priority the loop of c in -sw-sbd that occurs rapid current change in the switching. it is effective in reduci ng noise spikes caused by parasitic inductance. c out l sbd c in v in c out l sbd c in v in NJW4154 built-in sw NJW4154 built-in sw (a) buck converter sw on (b) buck converter sw off fig. 5. current loop at buck converter concerning the gnd line, it is preferred to separate the power system and the signal system, and use single ground point. the voltage sensing feedback line should be as far away as possible from the inductance. because this line has high impedance, it is laid out to avoid the influence noise caused by flux leaked from the inductance. fig. 6. shows example of wiring at buck conver ter. fig. 7 shows the pcb layout example. sw gnd in- v + c fb r2 c out l sbd NJW4154 c in r1 v out v in r l to avoid the influence of the voltage drop, the output voltage should be detected near the load. because in- pin is high impedance, the voltage detection resistance: r1/r2 is put as much as possible near ic(in-). separate digital(signal) gnd f rom pow er gnd (bypass capacitor) fig. 6. board layout at buck converter technical information njw 41 5 4 application manual
NJW4154 - 19 - ver.2013-03-29 application information (continued) hsop8 package to-252-5 package connect signal gnd line and powe r gnd line on backside pattern fig. 7. layout example (upper view) technical information njw 41 5 4 application manual c in c fb r fb r1 v out power gnd area feed back signal gnd out gnd in v in signal gnd area en/sync l c out r2 power good sbd c in2 1pin v out gnd out gnd in v in en/sync c in1 sbd l c fb r fb r1 r2 power gnd area c out feed back signal signal gnd area
NJW4154 - 20 - ver.2013-03-29 calculation of package power a lot of the power consumption of buck converter occurs from the internal switching element (power mosfet). power consumption of NJW4154 is roughly estimated as follows. input power: p in = v in i in [w] output power: p out = v out i out [w] diode loss: p diode = v f i l(avg) off duty [w] NJW4154 power consumption: p loss = p in ? p out ? p diode [w] where: v in : input voltage for converter i in : input current for converter v out : output voltage of converter i out : output current of converter v f : diode's forward saturation voltage i l(avg) : inductor average current off duty : switch off duty efficiency ( ) is calculated as follows. = (p out p in ) 100 [%] you should consider temperature derating to the calculated power consumption: p d . you should design power consumption in rated range referring to the power dissipation vs. ambient temperature characteristics (fig. 8). (*7): mounted on glass epoxy board. (76.2114.31.6mm:based on eia/jdec standard, 2layers) (*8): mounted on glass epoxy board. (76.2114.31.6mm:based on eia/jdec standard, 4layers) (for 4layers: applying 74.274.2mm inner cu area and a thermal via hall to a board based on jedec standard jesd51-5) (*9): mounted on glass epoxy board. (76.2114.31.6mm:based on eia/jdec standard size, 2layers, cu area 100mm 2 ) fig. 8. power dissipation vs. am bient temperature characteristics technical information njw 41 5 4 application manual NJW4154dl3 (to-252-5 package) power dissipation vs. ambient temperature (tj=~150c) 0 500 1000 1500 2000 2500 3000 3500 -50 -25 0 25 50 75 100 125 150 ambient temperature ta (c) power dissipation p d (mw) at on 4 layer pc board (*8) at on 2 layer pc board (*9) NJW4154gm1 (hsop8 package) power dissipation vs. ambient temperature (tj=~150c) 0 500 1000 1500 2000 2500 3000 -50 -25 0 25 50 75 100 125 150 ambient temperature ta (c) power dissipation p d (mw) at on 4 layer pc board (*8) at on 2 layer pc board (*7)
NJW4154 - 21 - ver.2013-03-29 application design examples buck converter application circuit ic input voltage : NJW4154gm1-a : v in =12v output voltage : v out =5v output current : i out =3a oscillation frequency : fosc=300khz sw pg gnd in- sbd NJW4154 v + en/ sy nc en/ sy nc high: on low: off (standby) pow er good (NJW4154gm1 only) c fb 15pf r2 160k ? c out 100 f/6.3v l 4.7 h/5.6a v in =12v c in1 10 f/50v r1 30k ? r fb 0 ? (short) v out =5v c in2 0.47 f/50v reference qty. part number description manufacturer ic 1 NJW4154 internal 3a mosfet sw.reg. ic new jrc l 1 cdrh127np-4r7n inductor 4.7 h, 5.6a sumida sbd 1 mbrs540t3g schottky diode 40v, 5a on semiconductor c in1 1 umk325bj106mm ceramic capacitor 3225 10 f, 50v, x5r taiyo yuden c in2 1 0.47 f ceramic capacitor 2012 0.47 f, 5 0 v, b std. c out 1 grm32eb30j107me16l ceramic capacitor 3225 100 f, 6 . 3 v, b murata c fb 1 15pf ceramic capacitor 1608 15pf, 50v, ch std. r fb 1 0 ? (short) optional ? r1 1 30k ? resistor 1608 30k ? , 1%, 0.1w std. r2 1 160k ? resistor 1608 160k ? , 1%, 0.1w std. technical information njw 41 5 4 application manual
NJW4154 - 22 - ver.2013-03-29 application characte ristics :NJW4154gm1-a at v out =5.0v setting [caution] the specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. the application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights. technical information njw 41 5 4 application manual output voltage vs. output current (a ver., v in =12v, ta=25c) 4 4.2 4.4 4.6 4.8 5 5.2 5.4 5.6 5.8 6 1 10 100 1000 10000 output current i out (ma) output voltage v out (v) f=300khz l=4.7 h efficiency vs. output current (a ver., v in =12v, v out =5v, ta=25c) 0 10 20 30 40 50 60 70 80 90 100 1 10 100 1000 10000 output current i out (ma) efficiency (%) f=300khz l=4.7 h

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